1. Field of the Invention
The present invention relates to an image processing apparatus capable of digital data format conversion between a first format, for example for image display, and a second format, for example for recording on a recording medium.
2. Related Background Art
There are recently developed apparatus capable of transmission or recording/reproduction of image data in digital form, thereby realizing image transmission without deterioration in S/N ratio, or image recording and reproduction without time-dependent deterioration. Such digital image processing apparatus is usually equipped with a data memory capable of storing at least one frame of image data to be handled or processed. The image data may be handled in various formats, such as a display format (or standard input/output format) in which the pixel signals (and image synchronization signals) are aligned in the sequence along the scanning direction, as in the output signals for a monitor or in the input signals from a camera, a recording format for a magnetic recording medium, or a transmission format according to the protocol specific to each communication channel. In the transmission or recording of an image, the data are shuffled and subjected to the addition of error correction codes. Also there are added a synchronization code SYNC and an identification code ID to each data block. FIG. 2(A) illustrates a basic format in which the pixel data are arranged in the order of horizontal and vertical scannings, and FIG. 2B illustrates a recording format on a magnetic tape in a digital VCR. The basic format shown in FIG. 2A corresponds to the horizontal and vertical scans in an image monitor.
Also the digital image processing apparatus is usually equipped with a data memory for temporarily storing the image data to be processed. Conventional digital image processing apparatus employs a circuit structure in which various circuit blocks such as input/output circuit, record/reproducing circuit, data memory etc. are combined through a bus, in order to enable common use of the data memory, thereby reducing the magnitude of hardware. A typical example of such digital image processing apparatus is the digital video cassette recorder (VCR).
FIG. 5 is a block diagram showing the basic structure of a conventional digital VCR, in which shown are an input/output terminal 10 to be connected to a transmission channel such as a public telephone network or a digital network, a television camera, an image monitor or a transmission interface; an input/output circuit 12 composed of an A/D converter, a D/A converter, an interface circuit etc.; a record/reproducing circuit 14 for effecting digital, recording of the image data on a magnetic tape 16 and reproduction of the signal recording on said magnetic tape 16; an encoding/decoding circuit 18 for effecting error correction encoding and decoding related to recording/reproduction; a data memory 20 utilized in the recording and reproduction by the record/reproducing circuit 14; error correction encoding and decoding by the encoding/decoding circuit 18, and input/output process by the input/output circuit 12; and a data bus for mutually connecting the circuits 12, 14, 18 and 20. The data flow in the above-explained configuration is shown in FIG. 6.
The above-explained conventional configuration is incapable, as will be apparent from FIG. 7, of effecting the writing and reading of the data memory through a same data bus at the same time, and is therefore associated with a drawback of a high access rate of the data bus and the data memory because of frequency writing and reading operations. In particular, a higher processing speed is required in case of real-time processing of the video signal.
Besides, if the writing and reading of a same data memory are conducted with different formats, such as the basic format and the recording format, there is inevitably required complex administration or control for said data memory. For simplifying such administration or control, an address generating circuit corresponding to the employed format has to be provided for each of the circuits connected to the data bus, so that the magnitude of the circuitry becomes inevitably large.
Furthermore, a configuration in which a data memory is commonly used through one or two data buses as in the conventional structure explained above, is associated with a drawback of an elevated access rate of the data bus and the data memory and an increased burden on the hardware, if there is required an image processing with a sequence of pixels different from that in the recording format or in the display (or transmission) format, for example encoding and decoding of the image data.
In addition, in recent years, the requirement for higher image quality necessitates a larger amount of data to be processed, and a faster data processing in the system is longed for because of an increase in the sampling rate.
An object of the present invention is to provide an image processing apparatus capable of individually or collectively resolving the drawbacks mentioned above.
Another object of the present invention is to provide an image processing apparatus capable of high-speed image processing.
Still another object of the present invention is to provide an image processing apparatus capable of data conversion into an image transmission format different from the image transmission format of a given image signal.
The above-mentioned objects can be attained, according to a preferred embodiment of the present invention, by an image processing apparatus comprising a first memory for storing data according to a first transmission format; a second memory for storing data according to a second transmission format different from said first transmission format; transfer control means for applying, at least in the data transfer from said first memory to said second memory, a predetermined process on the data read from said first memory; an input/output means connected with said first memory through a bus and adapted for effecting data input/output with an external equipment; and transmission means connected with said second memory through a bus and adapted for effecting data transmission.
Still another object of the present invention is to provide an image processing apparatus adapted for transferring image data in encoded form.
Still another object of the present invention is to provide an image processing apparatus adapted for use in a digital image recording apparatus.
Still another object of the present invention is to provide an image processing apparatus adapted for ADCT encoding.
Still other objects of the present invention, and the advantages thereof, will become fully apparent from the following description of embodiments, which is to be taken in conjunction with the attached drawings.